Consumer demands for higher capacity and/or faster operating electronic systems are driving the semiconductor industry to develop integrated circuits (ICs) that generally are denser and/or operate faster than the present generation ICs. These advanced design ICs have critical feature lengths typically less than 0.5 .mu.m, a length at which conventional optical lithography is typically at its operational limits. Optical lithography refers to a general technique for patterning a photoresist, typically a thin photosensitive polymer, using actinic radiation in the optical region of the electromagnetic spectrum to form a masking layer that selectively protects underlying material against chemical or physical attack during IC fabrication. In general, lithography in the semiconductor industry is the art of producing patterns in films (herein these films are known as resist material or simply resist) that can be used as a masking layer in processing integrated circuits. Each lithographic technique typically employs a characteristic actinic radiation.
The minimum feature length that can be attained in an IC typically depends on the wavelength of the actinic radiation used to expose the resist. To attain feature lengths smaller than 0.5 .mu.m (a process capable of producing feature lengths smaller than 0.5 .mu.m is herein referred to as a sub-half-micron process) generally requires the lithographic use of actinic radiation having wavelengths smaller than used in conventional optical lithography. As a result, innovative optical techniques and other lithographic technologies, utilizing radiation of appropriately small characteristic wavelengths, are being developed to produce these integrated circuits. The emerging technologies include, among others, electron beam (e-beam) direct write lithography, ion beam lithography, laser-based deep-uv lithography, and x-ray lithography. Of these technologies, e-beam lithography probably is the most mature, already having application to low volume IC production and to IC prototyping, though it has not yet been accepted for high volume production of integrated circuits, since the throughput of direct-write e-beam lithography is relatively slow. For a discussion of several emerging lithographic technologies, see P. Burggraaf, Semiconductor International, Vol. 10, No. 2, pp. 48-55, 1987.
The apparatus used in electron beam lithography is typically referred to as an electron beam (e-beam) exposure tool. The e-beam exposure tool provides a focused electron beam to form a pattern, typically, in a polymeric resist film or multilayer film structure on a semiconductor substrate, commonly known as a wafer. Typically, the pattern forms as a result of microstructural changes, such as polymer chain scission in positive resists or polymer chain cross-linking in negative resists, in response to irradiation by the electron beam. The patterns in the resist film produced by the microstructural changes have differing solubility rates corresponding to the electron beam exposure pattern. Appropriate solvents are used to process the desired pattern, by removing unwanted material layers on the wafer, forming a resist masking layer. E-beam lithography can be used to produce feature sizes of less than 0.5 .mu.m.
In sub-half-micron processes involved with fabricating an advanced IC, aligning different levels of the IC structure, i.e., centering a level to a previous level, is critical. Conventional alignment procedures for e-beam exposure tools typically use the e-beam tool as a scanning electron microscope (SEM) to image an alignment mark provided on a wafer. By referencing each level to the same alignment mark, the levels can be aligned to each other. Unfortunately, using the e-beam exposure tool in the SEM mode for imaging the wafer alignment mark frequently leads to electrically charging the wafer surface, due to the electron beam interacting with non-metallic materials on the surface. Surface charging typically results in image distortions which generally lead to alignment inaccuracies.
The charging effects can be substantially reduced or eliminated by providing a conductive top layer on the portions of the wafer to be aligned. This layer prevents charging by providing a conductive path to remove excess charge from the wafer surface. However, the presence of this conductive layer is typically temporary, involving additional processing steps to deposit and later remove it. Charging can also be substantially reduced by operating the exposure tool at electron energies where the secondary electron emission ratio is one (typically at 1 to 2 KeV). However, this procedure can expose the resist to irradiation before the wafer has been properly aligned and positioned, which can lead to unwanted microstructural changes in the resist material.